1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to the semiconductor memory device that operates in synchronization with a DRAM (Dynamic Random Access Memory) and/or an external clock such as a synchronous-type DRAM or a like.
The present application claims priority of Japanese Patent Application No. 2002-160846 filed on May 31, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 8 is a schematic block diagram showing an example of configurations of a conventional semiconductor memory device. The conventional semiconductor memory device shown in FIG. 8 is a synchronous-type DRAM which operates in a DDR (Double Data Rate) mode. An operation in the DDR mode represents an operation in which a DRAM can operate at a data transfer rate being two times faster than that of a conventional synchronous-type DRAM device by exerting control on inputting and outputting of data in synchronization with both rising and falling edges of a clock. The conventional semiconductor memory device described above includes an internal voltage generating circuit 1, inputting circuits 2 to 6, outputting circuits 7 and 8, a timing producing circuit 9, a command decoder (hereinafter may be referred simply to as a “CD”) 10, a latching circuit 11, a refresh counter 12, a column system controlling circuit 13, a row system controlling circuit 14, pre-decoder relieving circuits 15 and 16, a memory cell array (hereinafter may be referred simply to as an “MCA”) 17, a sense amplifier 18, a column decoder (hereinafter may be referred simply to as a “YDC”) 19, a row decoder (hereinafter may be referred simply to as an “XDC”) 20, a read system controlling circuit 21, a write system controlling circuit 22, a local input and output line 23, a sub-amplifier (hereinafter may be referred simply to as a “SubA”) 24, a main input and output line 25, a write amplifier (hereinafter may be referred simply to as a “WA”) 26, a main amplifier (hereinafter may be referred simply to as an “MA”) 27, a global input and output line 28, and FIFO (First In First Out) memories 29 and 30.
The internal voltage generating circuit 1 generates a required internal voltage by boosting and lowering a power source voltage VDD and a ground voltage VSS fed externally. The inputting circuit 2 performs waveform shaping or level conversion on a clock CK and a clock /CK fed externally and then outputs the obtained signal. The clock /CK has a same period as the clock CK and is a signal of opposite phase. The inputting circuit 3 performs waveform shaping or level conversion on a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, a chip select signal /CS, all being fed externally, and outputs the obtained signals. The row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, and chip select signal /CS are all active low. A high (“H”) level or a low (“L”) level of each of the row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, and chip select signal /CS indicates a command to determine an operation of the conventional semiconductor memory device. The inputting circuit 4 performs waveform shaping or level conversion on an address signal AD made up of a plurality of bits fed externally and outputs the obtained signal. The inputting circuit 5 performs waveform shaping or level conversion on a data strobe signal DQS fed externally and outputs the obtained signal. The data strobe signal DQS is a signal used to adjust timing with which data fed externally is captured in the inputting circuit 6. The inputting circuit 6 is controlled by the data strobe signal DQS fed from the inputting circuit 5 and performs waveform shaping or level conversion on data fed externally through a data input/output terminal DQ and outputs the obtained signal.
The outputting circuit 7 performs waveform shaping or level conversion on the data strobe signal DQS fed from the read system controlling circuit 21 and outputs the obtained signal. The outputting circuit 8 is controlled by the data strobe signal DQS fed from the read system controlling circuit 21 and performs waveform shaping or level conversion on data fed from the FIFO memory 30 and outputs the obtained signal. The timing producing circuit 9 produces various kinds of timing signals based on the clock CK and the clock/CK fed from the inputting circuit 2 and feeds them to the CD 10, latching circuit 11, column system controlling circuit 13, row system controlling circuit 14, read system controlling circuit 21, and write system controlling circuit 22. The CD 10 captures the row address strobe signal/RAS, column address strobe signal/CAS, write enable signal/WE, and chip select signal/CS, all being fed from the inputting circuit 3, according to a timing signal fed from the timing producing circuit 9, decodes commands defined by a combination of an “H” level and “L” level of these signals, produces various control signals according to decoded commands, and feeds the signals to the column system controlling circuit 13, row system controlling circuit 14, read system controlling circuit 21, and write system controlling circuit 22. The latching circuit 11 captures the address signal AD fed from the inputting circuit 4 according to a timing signal fed from the timing producing circuit 9 and, after having latched it, then feeds the obtained signal to the predecoder relieving circuits 15 and 16.
The refresh counter 12, based on a control signal fed from the row system controlling circuit 14, produces a row address for self-refreshing operations and feeds the obtained signal to the pre-decoder relieving circuit 16. The column system controlling circuit 13 captures a control signal fed from the CD 10 according to a timing signal fed from the timing producing circuit 9, produces a control signal used to control the pre-decoder relieving circuit 15, and feeds the obtained signal to the pre-decoder relieving circuit 16. The row system controlling circuit 14 captures a control signal fed from the CD 10 according to a timing signal fed from the timing producing circuit 9, produces a control signal to control the refresh counter 12 and the pre-decoder relieving circuit 16, and feeds the obtained signal to the refresh counter 12 and the pre-decoder relieving circuit 16. The pre-decoder relieving circuit 15 captures the address signal AD fed from the latching circuit 11 according to a control signal fed from the column system controlling circuit 13, decodes a column address from the captured address signal AD and feeds it to the YDC 19 and, at a same time, produces a redundant column address to reduce defective memory cells contained in memory cells making up the MCA 17 and feeds the obtained signal to the YDC 19. The pre-decoder relieving circuit 16 captures the address signal AD fed from the latching circuit 11 according to a control signal fed from the row system controlling circuit 14, decodes a column address from the captured address signal AD and feeds it to the XDC 20 and, at a same time, produces a redundant row address to reduce defective memory cells contained in memory cells making up the MCA 17 and feeds it to the XDC 20.
The MCA 17 has specified capacity, in which a plurality of memory cells MC are arranged, in a matrix form, in a vicinity of each point of intersection of a plurality of bit lines BL and a plurality of word lines WL. The sense amplifier 18 detects data read to a corresponding bit line BL from each of the memory cells MC, amplifies the data and feeds it to the SubA 24 through the local input and output line 23. The YDC 19 decodes a column address fed from the pre-decoder relieving circuit 15 and outputs a plurality of column selecting signals to put the sense amplifier 18 being connected to the corresponding bit line BL in the MCA 17 into a selected state. The XDC 20 decodes a row address fed from the pre-decoder relieving circuit 16 and puts the corresponding word line WL in the MCA 17 into a selected state.
The read system controlling circuit 21 captures a control signal fed from the CD 10 according to a timing signal fed from the timing producing circuit 9, produces a control signal to exert control on the outputting circuits 7 and 8, MA 27, and FIFO memory 30 and then feeds the obtained signal to the outputting circuits 7 and 8, MA 27, and FIFO memory 30. The write system controlling system 22 captures a control signal fed from the CD 10 according to a timing signal fed from the timing producing circuit 9, produces a control signal to exert control on the WA 26 and the FIFO memory 29, and feeds the obtained signal to the WA 26 and the FIFO memory 29. The SubA 24 amplifies data fed from the sense amplifier 18 through the local input and output line 23 and feeds the obtained signal to the MA 27 through the main input and output line 25. The WA 26 amplifies data fed from the FIFO memory 29 through the global input and output line 28 and feeds the obtained signal to the SubA 24 through the main input and output line 25. The MA 27 amplifies data fed from the SubA 24 through the main input and output line 25 and feeds the obtained signal to the FIFO memory 30 through the global input and output line 28. The FIFO memory 30 internally stores, in a first-in manner, data fed from the inputting circuit 6 in synchronization with the clock CK and, at a same time, reads, in a first-out manner, data internally stored in synchronization with the clock CK and feeds it to the WA 26 through the global input and output line 28. The FIFO memory 30 internally stores, in a first-in manner, data fed from the MA 27 in synchronization with the clock CK and, at a same time, reads, in a first-out manner, data internally stored in synchronization with the clock CK and feeds it to the outputting circuit 8.
Next, FIG. 9 is a schematic block diagram showing an example of configurations of the MA 27 and the FIFO memory 30 making up the conventional semiconductor memory device. The MA 27 is made up of sub-main amplifiers (hereinafter may be referred simply to as an “SMA”) 27a, 27b, 27c, and 27d whose number corresponds to a number of bits to be pre-fetched (described later) and, in FIG. 9, a case where 4-bit data is pre-fetched is illustrated. That is, the MA 27 includes four pieces of the SMAs 27a to 27d and 4-bit parallel data is amplified by each of the corresponding SMAs 27a to 27d. Each of the SMAs 27a to 27d amplifies each of corresponding complementary data MDT0 to MDT3 and MDTB0 to MDTB3 each having a small amplitude so as to become single data on a CMOS (Complementary Metal Oxide Semiconductor) level. Since the SMAs 27a to 27d have a same configuration, only the configuration of the SMA 27a is described hereinafter. The SMA 27a is made up of P-channel MOS transistors MP1 to MP5, N-channel MOS transistors MN1 to MN4, and the inverters INV1 to INV3. The MOS transistors MP1 to MP2 make up an input stage, the MOS transistors MP3 to MP4 and MN1 to MN3 make up an amplification stage, and inverters INV1 to INV3 and the MOS transistors MP5, and MN4 make up an output stage. Each of the SMAs 27a to 27d is connected to the FIFO memory 30 through each of global input and output lines 280 to 283 making up the global input and output line 28 shown in FIG. 8. The FIFO memory 30 is made up of flip-flops FF00 and FF01, FF10 and FF11, FF20 and FF21, and FF30 and FF31 being cascaded in two stages and corresponding to each of the SMA 27a to 27d, and of flip-flops FF40 and FF41 being cascaded in two stages and being connected respectively to output terminals of the flip-flops FF01, FF11, FF21 and FF31 being connected respectively to output terminals of the flip-flops FF00, FF10, FF20 and FF30. Each of the flip-flops FF00, FF10, FF20 and FF30 latches data output from each of corresponding SMA 27a to 27d using a common latch signal LT0. Each of the flip-flops FF01, FF11, FF21 and FF31, in order to convert 4-bit parallel data to 1-bit serial data, latches data output from each of the corresponding flip-flops FF00, FF10, FF20 and FF30 using latch signals LT1 to LT4 each being shifted by time corresponding to one cycle of each clock CK. Each of the flip-flops FF40 and FF41, in order to adjust timing such as latency, latches serial data using latch signals LT5 to LT6 each being shifted by time corresponding to one cycle of each clock CK and then feeds it to the outputting circuit 8.
FIG. 10 is a layout of a main portion showing an arrangement of circuits making up a first conventional semiconductor memory device. The first conventional semiconductor memory device has memory capacity of 512 M bytes being made up of four banks, eight pieces of data inputting and outputting pads (hereinafter may be referred simply to as a “DQ pad”) to input and output 8-bit data and being so constructed as to pre-fetch 4-bit data (that is, of a 4-bit pre-fetch structure). The four pieces of banks 310 to 313 are placed in an upper-left portion, lower left portion, upper right portion, and lower right portion of a semiconductor chip. Each of the banks 310 to 313 includes four pieces of MCAs 17 each having memory capacity of 32 M bits, two pieces of YDCs 19, two pieces of XDCs 20, two pieces of SubAs 24, eight pieces of MAs 27, or a like. FIG. 11 is an expanded diagram of a portion in which the MAs 27 in each of the banks 310 to 313 are connected to DQ pads 320 to 327 through global input and output lines 28, out of the layouts shown in FIG. 10. Moreover, in FIGS. 10 and 11, the FIFO memory 30 and the outputting circuit 8 placed in a back stage of the global input and output line 28 shown in FIG. 9 are not shown therein. The global input and output line 28 includes 16 pieces of first lines to connect the MAs 27 faced opposing one another, eight pieces of second lines to connect the first lines being corresponded to one another, and eight pieces of third lines one end of each of which is connected to each of the corresponding second lines and another end of each of which is connected to each of the corresponding DQ pads 320 to 327 being placed on a right side in FIG. 11 in wiring space provided in right and left directions in an approximately central portion of a conventional semiconductor chip. Since each of the global input and output lines 28 transfers 4-bit data, one piece of a line making up the global input and output lines 28 is made up of four sub-lines tied in a bundle and, in the wiring space shown in FIGS. 10 and 11, wiring using a total of 3 two pieces of lines on a bit level is carried out. Moreover, in FIGS. 10 and 11, each of numerals 0 to 7 written in each of rectangles for the MA 2700 to 2707, MA 2710 to 2717, MA 2720 to 2727, MA 2730 to 2737, and DQ pads 320 to 327 corresponds to numerical subscripts 0 to 7 of 8-bit DQ0 to DQ7 described later as in the case of a first digit numeral of subscripts of the MA 2700 to 2707, MA 2710 to 2717, MA 2720 to 2727, MA 2730 to 2737, and DQ pads 321 to 327. The same can be applied in FIGS. 12 and 13 described later. The MA 2700 to 2707, MA 2710 to 2717, MA 2720 to 2727, MA 2730 to 2737, when being collectively called, are simply represented as the MA 27. Similarly, the DQ pads 320 to 327, when being collectively called, are simply represented as the DQ pad 32. The same is applied in descriptions thereafter.
By employing such the layout described above, since a total length of the wiring for the global input and output lines 28 can be made shorter and the global input and output lines 28 can be made same in length and since the banks 310 to 313 are arranged in a cluster, lines and circuits employed in the above layout may be shared between the banks 310 to 313.
FIG. 12 is a layout of a main portion showing an arrangement of circuits making up a second conventional semiconductor memory device. The second conventional semiconductor memory device has memory capacity of 512 M bytes being made up of four banks, eight pieces of DQ pads and being so constructed as to pre-fetch 4-bit data. That is, the second conventional semiconductor memory device has four pieces of banks 310 to 313 being sequentially arranged in up-and-down directions on a conventional semiconductor chip and eight pieces of the DQ pads 320 to 327. Each of the banks 310 to 313 has memory capacity of 64 M bits and includes two pieces of MCAs 17, two pieces of YDCs 19, two sets of a combined XDC 20 and SubA 24, and eight pieces of MAs 27, or a like. The eight pieces of the MAs 27, in the bank 310, for example, are mounted in a manner that the MAs 2700, 2701, 2702, and 2703 are arranged sequentially from the left to the right in FIG. 12 in a lower portion of the MCA 17 being placed on a left side in FIG. 12 and, on the other hand, the MAs 2704, 2705, 2706, and 2707 are arranged sequentially from the right to the left in FIG. 12 in a lower portion of the MCA 17 being placed on a right side in FIG. 12. Moreover, in FIG. 12, the FIFO memory 30 and the outputting circuit 8 placed in a back stage of the global input and output line 28 shown in FIG. 9 are not shown therein. The global input and output line 28 includes 16 pieces of first lines to connect the MAs 27 faced opposing one another, eight pieces of second lines one end of each of which is connected to each of corresponding first lines and which extend toward an approximately central portion of the semiconductor chip and through wiring space being placed in up-and-down directions on the chip and another end of each of which is connected to a corresponding another first line of each of the MAs 27 faced opposing one another, and eight pieces of third lines one end of each of which is connected to each of corresponding second lines and another end of each of which is connected to each of corresponding DQ pads 320 to 327 being mounted on a right side in FIG. 12 in wiring space placed in left and right directions in the approximately central portion of the semiconductor chip. Since each of the global input and output lines 28 transfers 4-bit data, one piece of a line making up the global input and output line 28 is made up of four sub-lines tied in a bundle and, in the wiring space shown in FIG. 12. Wiring using a total of 3 two pieces of lines on a bit level is carried out in an upper portion of the DQ pads 320 to 327 in the wiring space in FIG. 12.
By employing such the layout described above, a load on the XDC 20 is reduced to a half when compared with the case shown in FIG. 10, which serves to speed up a process to be performed by the XDC 20.
FIG. 13 is a layout of a main portion showing an arrangement of circuits making up a third conventional semiconductor memory device. The third conventional semiconductor memory device has memory capacity of 512 M bytes being made up of four banks, eight pieces of DQ pads and being so constructed as to pre-fetch 4-bit data. In the third conventional semiconductor memory device, a semiconductor chip is divided into two portions, one being a left portion and another being a right portion and sub-banks 310a, 311a, 312a, 313a each making up four pieces of banks 310 to 313 are sequentially arranged respectively in an upper left portion, lower left portion, upper right portion, and lower right portion in a left half of the semiconductor chip and sub-banks 310b, 311b, 312b, 313b each making up four pieces of banks 310 to 313 are sequentially arranged respectively in an upper left portion, lower left portion, upper right portion, and lower right portion in a right half of the semiconductor chip. The third conventional semiconductor memory device also has eight pieces of DQ pads 320 to 327. Each of the sub-banks 310a, 311a, 312a, and 313a and each of the sub-banks 310b, 311b, 312b, and 313b have one piece of the MCA 17 having memory capacity of 64 bits, one piece of the YDC 19, and one piece of the XDC 20, and four pieces of MAs 27 or a like. In the sub-banks 310a and 312a, an MA 2700, MA 2701, MA 2702, MA 2703 making up the MA 27 and an MA 2720, MA 2721, MA 2722, and MA 2723 also making up the MA 27 are arranged from an upper direction toward a down direction in wiring space being placed in up-and-down directions in an approximately central portion of a left half of a semiconductor chip and, on the other hand, in the sub-banks 311a and 313a, an MA 2710, MA 2711, MA 2712, MA 2713 making up one of four pieces of the MA 27 and an MA 2730, MA 2731, MA 2732, and MA 2733 also making up one of four pieces of the MA 27 are arranged from a down direction toward an upper direction in wiring space being placed in up-and-down directions in the approximately central portion of the left half of the semiconductor chip. Moreover, in the sub-banks 310b and 312b, an MA 2704, MA 2705, MA 2706, MA 2707 making up one of four pieces of the MA 27 and an MA 2724, MA 2725, MA 2726, and MA 2727 also making up one of four pieces of the MA 27 are arranged from an upper direction toward a down direction in wiring space being placed in up-and-down directions in an approximately central portion of a right half of the semiconductor chip and, on the other hand, in the sub-banks 311b and 313b, an MA 2714, MA 2715, MA 2716, MA 2717 making up the MA 27 and an MA 2734, MA 2735, MA 2736, and MA 2737 also making up the MA 27 are arranged from a down direction toward an upper direction in wiring space being placed in up-and-down directions in the approximately central portion of the right half of the semiconductor chip.
In FIG. 13, the SubA 24 and the FIFO memory 30 and the outputting circuit 8 being placed in a back stage of the global input and output line 28 shown in FIG. 9 are not shown therein. In a left half of the semiconductor chip, the global input and output line 28 is made up of eight pieces of first lines each connecting the MAs 27 faced opposing one another, four pieces of second lines each connecting the first lines being corresponded to each other, and four pieces of third lines being placed toward an approximately central center of wiring space being placed in left and right directions in an approximately central portion of the semiconductor chip, one end of each of which is connected to each of corresponding second lines and another end of each of which is connected to each of the corresponding DQ pads 320 to 323 being placed on a slightly right side in an approximately central portion of the semiconductor chip. On the other hand, in a right half of the semiconductor chip, the global input and output line 28 is made up of eight pieces of first lines each connecting the MAs 27 faced opposing one another, four pieces of second lines each connecting the first lines being corresponded to each other, and four pieces of third lines one end of each of which is connected to each of corresponding second lines and another end of each of which is connected to each of the corresponding DQ pads 320 to 323 being placed at a right end of wiring space being placed in left and right directions in an approximately central portion of the semiconductor chip. Since each of the global input and output lines 28 transfers 4-bit data, one piece of a line making up the global input and output lines 28 is made up of four sub-lines tied in a bundle and in the wiring space being placed in left and right directions in an approximately central portion of the semiconductor chip shown in FIG. 13, wiring using a total of sixteen lines on a bit level is carried out.
A reason why the DQ pads 320 to 327 in the above-described first, second, and third conventional semiconductor memory devices are arranged from the left to the right in FIGS. 10, 12, and 13 in the right half of the wiring space being placed in the left and right directions in an approximately central portion of the semiconductor chip is as follows. That is, a pin arrangement for a synchronous-type DRAM being operable in a DDR mode is normalized by JEDEC (Joint Electron Device Engineering Council) serving as an organization for standardization as shown in FIG. 14. In FIG. 14, the pin arrangement marked by “×8 (256 M/512 M) bit” corresponds to the layouts shown in FIGS. 10, 12, and 13 in which each of pins having its pin numbers 2, 5, 8, 11, 56, 59, 62, and 65 each being called the DQ0 to DQ7 as pin names is connected to each of the DQ pads 320 to 327.
For this reason, the global input and output line 28 has a largest wiring length out of data buses and large loads and, if a length of a longer side of the semiconductor chip is 12 mm, a length of each of the global input and output lines 28 is 6 mm, which causes inconvenience described below. That is, in the first conventional semiconductor memory device shown in FIG. 10, a length of each of the global input and output lines 28 to connect the MA 2730 to the DQ pad 320 is different greatly from a length of each of the global input and outlines 28 to connect the MA 2700 to the DQ pad 320. Thus, due to a difference in length between the global input and output lines 28, data transmitted through the global input and output line 28 from the MA 2700 to the DQ pad 320 arrives later than data transmitted through the global input and output line 28 from the MA 2730 to the DQ pad 320. Such a variation in delayed time in data transmission is called “skew”. FIG. 15 is a timing chart showing such the delayed time as described above. Let it be assumed here that a period of the clock CK fed externally shown by (1) in FIG. 15 is 2 ns (nanoseconds). When a read command READ being one of commands CMD decoded by the CD 10 shown in FIG. 8 is fed in synchronization with the clock CK and with timing shown by (2) in FIG. 15 and when a column selecting signal YS is fed with timing shown by (3) in FIG. 15 from the pre-decoder relieving circuit 15 to the TDC 19, complementary data MDT0 to MDT3 and MDTB0 to MDTB3 each having a small amplitude (only data MDT3 is shown by (4) in FIG. 15) are fed. At this point, there is almost no difference in arriving time among the complementary data MDT0 to MDT3 and MDTB0 to MDTB3 each having a small amplitude to be fed to each of the MAs 27.
However, since the length of each of the global input and output lines 28 to connect the MA 2730 to the DQ pad 320 is different from the length of each of the global input and output lines 28 to connect the MA 2700 to the DQ pad 320, there occurs a difference of time TD in arriving time, as shown by (5) and (6) in FIG. 15, between data DT3 which reaches the DQ pad 320 through the global input and output line 28 after the complementary data MDT3 and MDTB3 each having a small amplitude have been amplified in the MA 2730 and data DT0 which reaches the DQ pad 320 through the global input and output line 28 after the complementary data MDT0 and MDTB0 each having a small amplitude have been amplified in the MA 2730. This time TD, that is, the skew is about 3 ns. As a result, a margin TM used for a latching operation by a latch signal LT (shown by (7) in FIG. 15) fed in the FIFO memory 30 externally becomes 1 ns or less. This time TD is a main factor to determine a limit of operational frequencies of the synchronous-type DRAM. An inconvenience occurs that, if data being stored in each of the MCAs 17 making up different banks is read, due to the skew in data transmission among banks, timing with which data is latched cannot be ensured.
In this respect, a method for ensuring the margin TM may be thought out in which a technique of latching data of a plurality of bits is further developed in the FIFO memory 30 which has been worked out originally to solve such the problem as above, that is, in which a number of bits of data to be latched in the FIFO memory 30 is increased so as to be 8 bits (that is, in the case of an 8-bit pre-fetch structure), 16 bits (that is, in the case of a 16-bit pre-fetch structure), or more. That is, if a period tCK of a clock CK is 2 ns, in the case of a synchronous-type DRAM of 4-bit pre-fetch structure called a “DDRII” out of the synchronous-type DRAMs being operable in a DDR mode, a transfer period in the global input and output line 28 is 4 ns. However, the transfer period in the global input and output line 28 in the case of the synchronous-type DRAM of 8-bit pre-fetch structure is 8 ns and the transfer period in the global input and output line 28 in the case of the synchronous-type DRAM of 16-bit pre-fetch structure is 16 ns. However, the above method has a disadvantage. That is, if the number of bits of data to be latched is increased as above, since a number of the global input and output lines 28 becomes 6 four pieces, 12 eight pieces, or more, wiring space, placed in left and right directions in an approximately central portion in a semiconductor chip, being wider than wiring space (about 500 μm) being employed at present which is already sufficiently wide, is required, which causes an area of the semiconductor chip to be the wider. Moreover, even if this method is employed, it is impossible to properly cope with future possible speedup of a clock. Moreover, in order to reduce skew, it can be thought out that a repeater to amplify data is to be placed at some midpoint in the longer global input and output line 28. However, it is structurally difficult to place such the repeater in the DRAM being operable in the DDR mode due to restriction on an area of a semiconductor chip or a like.
The second conventional semiconductor memory device shown in FIG. 12 has a same disadvantage as the first conventional semiconductor device shown in FIG. 10 in that a total length of the global input and output line 28 is as long as about 20 mm and differences in length among the global input and output lines 28 used to connect each of the MAs 27 to each of the corresponding DQ pads 32 are large (about 9 to 11.5 mm). Moreover, the third conventional semiconductor memory device shown in FIG. 13 also has same disadvantages as the first and second conventional semiconductor memory device in that, in addition to the problems seen in the first and second semiconductor memory device, as is apparent from FIG. 13, same problems occur since there are differences in length among the global input and output lines 28 used to connect each of the MAs 27 to each of the DQ pads 320 to 323 and the global input and output lines 28 used to connect each of the MAs 27 to each of the DQ pads 324 to 327.
The inconveniences described above occur in a DRAM which enables high-speed data transfer called a “Rambus DRAM” (trade name) in a same manner as above. That is, in the Rambus DRAM being available at present, a frequency of data to be transferred through a global input and output line is 100 MHz being lower than that employed in the DRAM being operable in the DDR mode and reduction of the time TD described above is not required and therefore any countermeasures have not been taken. However, since, in the above Rambus DRAM, DQ pads are mounted and 8-bit data is latched in a FIFO memory, when the number of the frequency being employed now is increased for speed-up of the data transfer in the future, it is inevitable that the same problems as above occur. Here, for reference, one example of configurations of the Rambus DRAM is explained. That is, a Rambus DRAM has memory capacity of 288 M bits and, if it is of an 18-bit DQ and 8-bit pre-fetch structure, its clock frequency is 400 MHz, its operational frequency is 800 MHz, a frequency of data to be transferred through a global input and output line is 100 MHz, and a number of the global input and output lines is 144 (in the case of common use for reading and writing).